Meta Platforms has revealed technical and deployment plans for its next generations of custom artificial intelligence processors, designated MTIA 450 and MTIA 500. The upcoming silicon, code-named Arke and Astrid respectively, will enter the company's global data centers throughout 2027 as part of a long-term effort to optimize large-scale inference workloads.
The announcement underscores Meta's strategy to expand its in-house Meta Training and Inference Accelerator (MTIA) family alongside third-party hardware. According to executive leadership, the new chips aim to provide superior energy efficiency and performance per dollar compared to existing off-the-shelf commercial accelerators.
Meta MTIA Arke Astrid AI Chips: Strategic Roadmap for 2027
Meta plans to initiate data center installation of its third-generation custom processor, the MTIA 450 (Arke), during the first half of 2027. That rollout will be followed late in the year by the fourth-generation MTIA 500 (Astrid), which is finalizing design validation and will see significantly wider deployment across the company's infrastructure.
Both silicon projects focus on general-purpose AI inference, handling tasks such as content recommendation algorithms and running generative AI models. Meta confirmed that early physical samples of the Arke chip delivered from fabrication in early September performed within two to three percent of pre-silicon digital simulations, running internal workloads on day one.
Meta Expands In-House AI Hardware Portfolio
Since detailing its custom silicon roadmap in 2023, Meta has iteratively upgraded its hardware architectures to handle increasingly complex neural network demands. While earlier iterations focused primarily on ranking and recommendation workloads, the newer MTIA models expand support to general Generative AI inference tasks.
The hardware expansion comes as major technology hyperscalers invest heavily in custom application-specific integrated circuits (ASICs) to control physical infrastructure costs. Industry shifts toward custom silicon have gained momentum across the tech sector, mirroring moves like OpenAI's planned production of next-gen AI processors to diversify compute supply chains.
To keep the engineering team focused on high-yield, cost-effective inference targets, Meta chose to cancel a planned dual-purpose processor code-named Olympus. Executives noted that combining training and inference capabilities into a single package would have increased unit costs by roughly 30 percent, which proved impractical given the massive scale of their scheduled data center builds.
Specifications of MTIA 450 Arke and MTIA 500 Astrid
The MTIA 450 (Arke) features targeted architecture tailored for large language model inference. During initial bring-up testing, engineering teams verified the silicon by running Meta's proprietary models alongside open architectures from DeepSeek and Alibaba.
The upcoming MTIA 500 (Astrid) introduces further efficiency gains and refined interconnect bandwidth. Both designs incorporate high-bandwidth memory (HBM) architectures to overcome memory bus bottlenecks when executing multi-billion-parameter inference tasks. By scaling these architectures, Meta has committed to deploying more than one gigawatt of homegrown compute capacity within a 12-month period starting in 2027.
Manufacturing Partnerships with Broadcom and TSMC
Meta's custom silicon development relies heavily on key strategic semiconductor partnerships. ASIC design specialist Broadcom assists Meta's engineering team with physical implementation, IP integration, and high-speed networking co-design.
Production is handled by foundry partner Taiwan Semiconductor Manufacturing Co. (TSMC), which manufactures the chips on leading-edge process nodes. The collaboration follows broader trends in customized enterprise computing, similar to how NVIDIA invested in MediaTek for AI chip co-development to expand interconnect ecosystems.
Yee Jiun Song, Meta's Vice President of Engineering overseeing the custom silicon program, highlighted the calculated approach to iteration: "Each one takes on a little bit more risk technologically, and gets us better performance per watt of energy and per dollar spent," Song explained in recent interviews.
Reducing Data Center Reliance on External GPUs
Power consumption and raw capital costs represent the primary bottlenecks for hyper-scale AI operations. By tailoring MTIA chips directly to its internal model software stacks, Meta expects to extract higher execution efficiency than general-purpose graphics processors currently on the commercial market.
However, Meta emphasized that homegrown chips will complement rather than completely replace commercial graphics hardware. The company remains one of the largest buyers of flagship accelerators from vendors like NVIDIA and AMD to handle intensive model pre-training. Similar hybrid infrastructure deployments are active globally, such as when AMD and Cisco deployed Instinct MI355X AI infrastructure for heavy compute workloads.
At the consumer hardware level, the semiconductor industry is seeing widespread adjustments driven by rising component complexity, from enterprise server rooms down to client devices where Qualcomm raised chip prices ahead of new AI PC launches. Meanwhile, raw demand for graphics processing hardware remains robust, as reflected in reports where desktop GPU shipments hit four-year highs across consumer markets.
Meta's Superintelligence Labs continues to work directly alongside hardware engineers to fine-tune future MTIA silicon against upcoming AI software requirements. If data center power demand and model usage remain on their current growth trajectories, Meta expects its internal custom silicon deployment rates to accelerate further beyond the initial gigawatt milestone.
In summary, Meta's introduction of the MTIA 450 Arke and MTIA 500 Astrid marks a pivotal step in its custom silicon strategy. By targeting cost-efficient inference at gigawatt scale through partners Broadcom and TSMC, Meta aims to secure greater operational control and cost control over its long-term AI infrastructure.
