At the Hot Chips 2026 conference, wafer-scale AI hardware pioneer Cerebras Systems presented technical details surrounding its new Nexus system architecture and revealed a multi-generational roadmap culminating in 3D stacked DRAM integration. The presentation highlighted how the company's CS-4 system leverages Nexus to triple rack-scale performance while laying the groundwork for future wafer-scale engines.
By advancing from single-wafer server nodes to highly integrated rack-scale systems and true vertical packaging, Cerebras aims to maintain its performance advantages in real-time artificial intelligence model serving and large language model inference. The announcements underscore an industry-wide effort to solve persistent memory bandwidth bottlenecks and scaling constraints inherent to traditional GPU clusters.
cerebras nexus stacked dram hot chips 2026
During Hot Chips 2026, Cerebras showcased its Nexus platform architecture alongside a ambitious hardware roadmap that integrates 3D stacked DRAM in its upcoming CS-6 generation. Nexus serves as the physical and electrical foundation for the CS-4 rack-scale platform, housing three Wafer Scale Engine 3 Turbo (WSE-3T) processors in a unified enclosure. Looking further ahead, Cerebras revealed that its CS-6 system will incorporate 3D stacked DRAM directly on top of logic and SRAM silicon, expanding memory capacity while maintaining ultra-fast token generation speeds.
Cerebras Outlines Nexus Architecture at Hot Chips 2026
The newly detailed Nexus platform represents a structural shift in how Cerebras deploys its massive wafer-scale processors. Rather than placing individual processors inside isolated chassis, Nexus provides a modular rack implementation built around independent compute, power, and high-speed I/O domains.
Compute density within the Nexus rack is anchored by rear-mounted units referred to as Wafer-Scale Backpacks. Each backpack connects vertically to the primary power array, combining direct-to-chip liquid cooling manifolds, point-of-load power conversion stages, and control electronics directly behind the silicon wafer. This design eliminates thousands of external cables that are typical in traditional multi-GPU clusters, such as those described in NVIDIA Unveils Groq 3 LPX AI Inference Rack Architecture at Hot Chips.
By isolating the core compute layer from the structural power frame, Cerebras reduced system component counts by 50 percent and improved automated assembly during manufacturing. Data center deployments can now be completed in hours rather than days, while overall system reliability is boosted by reducing mechanical points of failure.
Boosting Rack-Scale Throughput with CS-4 Systems
The CS-4 is the first commercial deployment built on top of the Nexus rack design. Housing three WSE-3T processors, the system delivers an impressive 750 PFLOPS of sparse AI compute along with 129.6 petabytes per second of memory bandwidth and 7.2 terabits per second of system I/O.
Compared to the previous-generation CS-3, the CS-4 offers up to twice the token generation speed and up to a 10-fold increase in throughput per watt. In high-concurrency inference workloads involving large models, Cerebras claims the CS-4 can achieve up to 30 times the inference performance of traditional GPU-based racks. Inter-wafer communication latency drops as low as two microseconds within the Nexus frame, allowing clusters to efficiently process frontier models with tens of trillions of parameters.
CS-6 Wafer Engine Roadmap Incorporates 3D Stacked DRAM
While the CS-4 focuses on system-level integration and the upcoming CS-5 will boost token generation speed, the future CS-6 system marks a critical transition in semiconductor packaging. Cerebras revealed that CS-6 will implement 3D stacked DRAM directly over its wafer-scale engines.
Until now, Cerebras has relied exclusively on massive arrays of on-wafer SRAM to deliver high memory bandwidth. While SRAM offers unmatched speed, it occupies valuable silicon area on a 300mm wafer. By vertically stacking DRAM on top of the logic layer through advanced 3D packaging, Cerebras can reallocate portion of the main wafer to additional compute cores while dramatically increasing total memory capacity.
This shift reflects broader trends across the computing industry, where vertical chiplet integration is becoming standard for server processors. For example, technical sessions at the event also highlighted structural packaging innovations such as Fujitsu Details 144-Core Monaka Server CPU with 3D Cache Stacking at Hot Chips and Arm Details AGI Server Processor with Dual 70-Core Chiplets at Hot Chips 2026.
Addressing Memory Bandwidth and Latency Bottlenecks for AI Inference
The push toward 3D stacked DRAM is driven by the soaring memory demands of enterprise AI workloads. Large language models require extensive memory footprints to hold model weights, while real-time inference session demands grow rapidly due to expanding Key-Value (KV) caches.
Standard GPU systems attempt to satisfy these demands by pairing processors with High Bandwidth Memory (HBM) modules on an interposer. However, interconnect limits and external bus latencies can bottleneck performance when handling long-context reasoning tasks. Global supply pressures and elevated memory pricing have further emphasized the need for efficient architectures, as noted in South Korea DRAM Export Prices Reach Record $92,183 Per Kilo.
By bringing DRAM directly onto the wafer-scale engine via vertical 3D interconnects, Cerebras aims to deliver high-capacity memory without sacrificing its ultra-low latency advantage. The company noted that the CS-6 architecture will feature a yield-resilient structure, vertical power delivery, and fully integrated liquid cooling to manage the thermal density of stacked silicon.
Industry reactions to the announcement have been largely positive, with analysts pointing out that combining rack-scale disaggregation with 3D memory stacking positions Cerebras as a key competitor against traditional GPU vendors in high-throughput token production.
In summary, the Hot Chips 2026 announcements demonstrate how Cerebras plans to maintain its momentum in frontier AI hardware. Through the Nexus system architecture in CS-4 and the planned 3D stacked DRAM in CS-6, the company is systematically removing physical and memory bottlenecks to enable faster, more efficient AI inference at scale.
