Montage Technology Begins Trial Production of CXL 3.2 MXC Chip

Montage Technology has officially announced the industry-first trial production of its Compute Express Link (CXL) 3.2 Memory eXpander Controller (MXC) chip. Designed to tackle growing memory bottlenecks in artificial intelligence, cloud computing, and enterprise data centers, the new silicon marks a key milestone toward commercializing composable memory architectures.

By converting host-side CXL memory requests into direct DDR commands in real time, the controller enables system architects to expand memory capacity and pool resources far beyond traditional server physical limits. The breakthrough device arrives at a moment when memory bandwidth and capacity constraints have become primary limiting factors for large-scale AI training and inference models.

Montage Technology CXL 3.2 DDR5 MXC Chip and Trial Production Summary

The trial production of the Montage Technology CXL 3.2 DDR5 MXC chip represents an important advancement in next-generation server memory controller technology. Designated as part number M88MX6852, the component is an advanced CXL Type 3 DRAM controller that leverages a PCIe 6.x physical layer to deliver data transfer rates of up to 64 GT/s per link. It incorporates dual DDR5 memory controllers capable of supporting speeds up to 8000 MT/s, establishing a high-throughput bridge between system processors and memory expansion modules.

Compliance with CXL Type 3 specifications allows the controller to support both the CXL.mem and CXL.io protocols. This dual-protocol approach ensures low-latency memory access alongside standardized device discovery, configuration, and robust system management. By enabling disaggregated memory pooling, servers can share dynamic RAM across interconnected compute nodes, optimizing utilization rates and substantially lowering the total cost of ownership for cloud operators.

Dual DDR5 Controller Architecture and PCIe 6.x Bandwidth

At the technical core of the chip lies a highly integrated system-on-chip design built for maximum throughput and minimal processing overhead. The inclusion of a PCIe 6.2 physical layer allows the chip to operate as an x8 connection or split into dual x4 links, maintaining flexibility for varied server topologies. Coupled with host-side link speeds reaching 64 GT/s, the controller doubles the physical interface bandwidth offered by previous-generation PCIe 5.0 and CXL 2.0 implementations.

To match this immense interface speed on the backend, Montage integrated two independent JEDEC-compliant DDR5 memory controllers. Supporting advanced memory speeds up to DDR5-8000, the controller can drive standard RDIMMs, UDIMMs, or customized on-board DRAM configurations. The architecture includes dedicated PCIe 6.x PHY and DDR5 PHY layers, along with dual embedded RISC-V processor subsystems that oversee local management tasks, power sequencing, and telemetry functions.

System designers can deploy the component across diverse physical form factors. These include standard PCIe Add-in Cards (AIC) and Enterprise and Datacenter Standard Form Factor (EDSFF) modules. The design natively supports SMBus, I3C, I2C, SPI, and UART management interfaces, allowing broad telemetry collection and seamless interaction with baseboard management controllers.

Addressing Server Memory Expansion and Latency Limits

Modern high-performance computing platforms face a strict structural limitation known as the memory wall. As CPU and GPU core counts scale rapidly, the available physical pin space on processor packages cannot keep pace with the demand for extra memory channels. Traditional direct-attached DIMM slots quickly hit physical layout and signal integrity boundaries, leaving individual compute cores starvation-prone during massive parallel processing tasks.

CXL technology provides a cache-coherent interconnect that bypasses these physical pin limits by extending host memory across high-speed fabric buses. By offloading host memory requests directly to the dedicated MXC device, servers gain access to multi-terabyte memory pools without sacrificing cache coherency. The ultra-low conversion delay built into the hardware translation pipeline ensures that attached DDR5 memory responds with latency characteristics suitable for direct CPU access.

This dynamic memory expansion mechanism is particularly vital for emerging application landscapes. Large language model training, real-time analytics, vector databases, and multi-tenant virtualization platforms benefit significantly from disaggregated memory pools. Rather than over-provisioning expensive physical memory inside every individual server chassis, data center engineers can allocate memory chunks on demand from shared memory pools, eliminating stranded memory capacity.

Industry Adoption and CXL Memory Controller Roadmap

Montage Technology has been at the forefront of the CXL ecosystem since the protocol's inception, previously releasing early-generation controllers compliant with CXL 1.1, 2.0, and 3.1 standards. The transition of the M88MX6852 silicon into trial production signifies that the CXL 3.2 framework is moving rapidly toward broad commercial deployment.

"The trial production of the CXL 3.2 MXC chip marks an important milestone in Montage Technology's pursuit of CXL innovation and commercialization," stated Stephen Tai, President at Montage Technology. "As memory demands continue to surge in the AI era, we are providing our customers with high-bandwidth, large-capacity, and highly reliable memory expansion solutions, accelerating the large-scale adoption of CXL in data center and AI infrastructure."

To support hardware integrators during this trial phase, Montage is providing a comprehensive software development kit alongside comprehensive signal analysis and diagnostic testing tools. Initial hardware validation efforts have already yielded positive results. Major memory vendors, including Samsung and SK Hynix, have completed early compatibility tests using next-generation memory modules paired with the controller. Furthermore, the solution demonstrates broad cross-platform interoperability with leading server enterprise hardware, including Intel Xeon and AMD EPYC platform architectures.

As trial production progresses, full-scale mass production will mark a major step in fulfilling the industry's vision of fully composable, memory-centric infrastructure for next-generation computing.